Experienced Verification Engineer - System IP

• Contribute to System IP microarchitecture specification and design
• Contribute in SystemVerilog, C and C++ to verification, modelling and debug to achieve required quality levels (SystemVerilog/UVM, C, C++, scripting)
• Propose and prototype new ways and define methodologies to reach goals more efficiently
• Own and develop verification plans, environments, determine the best approach
• Work closely with engineers across design, performance modelling, validation, and implementation to meet all functional requirements, performance, power and area goals

Required Skills and Experience:

• Master’s degree in Electrical Engineering or Computer Engineering strongly preferred, Bachelor's degree along with shown related experience may be substituted
• Experience in object oriented software development (C++ or SystemVerilog preferred)
• Interest in and theoretical knowledge of digital circuits, FPGAs, embedded SW (C)
• Enthusiasm and curiosity to learn new things and ways
• Post-degree work experience

“Nice To Have” Skills and Experience:

• Exposure to all stages of the product development cycle: initial concept, specification, implementation and testing, documentation, release and support
• Experience with block level RTL design and verification of non-trivial ASIC (or FPGA) developments; SystemVerilog preferred
• Scripting, e.g. Linux, Bash, Python, etc.
• Ability to travel occasionally for training and customer meetings
• Proficiency in both written and oral English